AD7606時(shí)序控制及PWM輸出Verilog代碼Quartus仿真

名稱：AD7606時(shí)序控制及PWM輸出Verilog代碼Quartus仿真

軟件：Quartus

語言：Verilog

代碼功能：

AD7606B輸入,(4800-輸入)/8(仿真時(shí)=學(xué)號(hào)后3位),PWM輸出(600=100%)。

每位交一個(gè)pdf文檔,包括方案分析(聯(lián)系應(yīng)用)、FPGA連線圖、VHD文件(含注釋)、編譯報(bào)告、完整功能仿真結(jié)果(詳加說明)、亮點(diǎn)(研究性內(nèi)容)、參考文獻(xiàn)(規(guī)范引用)。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. 仿真圖

整體仿真圖

AD7606B模塊仿真

PWM模塊仿真

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
???USE?ieee.std_logic_arith.all;
???
--adc7606b，硬件模式，并行輸出
ENTITY?AD7606b_control?IS
???PORT?(
??????sys_clk???:?IN?STD_LOGIC;--時(shí)鐘
??????reset?????:?IN?STD_LOGIC;--復(fù)位
??????AD7606_RST???:?OUT?STD_LOGIC;--高電平復(fù)位
??????AD7606_RD????????:?OUT?STD_LOGIC;--低電平讀
??????AD7606_CVT???:?OUT?STD_LOGIC;--convst
??????AD7606_CS????????:?OUT?STD_LOGIC;--低電平使能
??????AD7606_OS????????:?OUT?STD_LOGIC_VECTOR(2?DOWNTO?0);--輸出低電平
??????AD7606_BUSY??????:?IN?STD_LOGIC;--忙
??????AD7606_D?????????:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);--并行輸入AD
??????channel_one???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道1
??????channel_two???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道2
??????channel_three???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道3
??????channel_four???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道4
??????channel_five???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道5
??????channel_six???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道6
??????channel_seven???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--輸出通道7
??????channel_eight???????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)?--輸出通道8
???);
END?AD7606b_control;
ARCHITECTURE?beh?OF?AD7606b_control?IS
???type?state_type?is?(s_start?,s_gen_cvt,s_get_busy?,s_rd_data?,s_sample_da?);
???SIGNAL?current_state?????:?state_type;
???SIGNAL?next_state???????:?state_type;
???SIGNAL?cvt_cnt???????:?STD_LOGIC_VECTOR(1?DOWNTO?0);
???SIGNAL?channel_cnt????????:?STD_LOGIC_VECTOR(2?DOWNTO?0);
???SIGNAL?AD7606_CVT_s?:?STD_LOGIC;
???SIGNAL?AD7606_read??????:?STD_LOGIC;
???SIGNAL?read_over??????????:?STD_LOGIC;
???SIGNAL?sample_pulse???:?STD_LOGIC;
???SIGNAL?sample_cnt???????:?integer;
BEGIN
???--狀態(tài)切換
???PROCESS?(sys_clk,?reset)
???BEGIN
??????IF?(reset=?'0')?THEN
?????????current_state?<=?s_start;
??????ELSIF?(sys_clk'EVENT?AND?sys_clk?=?'1')?THEN
?????????current_state?<=?next_state;
??????END?IF;
???END?PROCESS;
???
???--狀態(tài)控制
???PROCESS?(current_state,?sample_pulse,?AD7606_CVT_s,?AD7606_BUSY,?read_over)
???BEGIN
??????next_state?<=?current_state;
??????CASE?current_state?IS
?????????WHEN?s_start?=>
????????????IF?(sample_pulse?=?'1')?THEN--開始采樣
???????????????next_state?<=?s_gen_cvt;
????????????END?IF;
?????????WHEN?s_gen_cvt?=>
????????????IF?(AD7606_CVT_s?=?'1')?THEN--高電平后跳轉(zhuǎn)
???????????????next_state?<=?s_get_busy;
????????????END?IF;
?????????WHEN?s_get_busy?=>
????????????IF?((NOT(AD7606_BUSY))?=?'1')?THEN
next_state?<=?s_rd_data;--空閑后開始讀數(shù)
????????????END?IF;
?????????WHEN?s_rd_data?=>--讀數(shù)
????????????next_state?<=?s_sample_da;
?????????WHEN?s_sample_da?=>
????????????IF?(read_over?=?'1')?THEN--讀完
???????????????next_state?<=?s_start;
????????????END?IF;
?????????WHEN?OTHERS?=>
????????????next_state?<=?s_start;
??????END?CASE;
???END?PROCESS;
???
???--輸出控制
???PROCESS?(sys_clk,?reset)
???BEGIN
??????IF?(reset=?'0')?THEN
?????????AD7606_CS?<=?'1';
?????????AD7606_CVT_s?<=?'0';
?????????cvt_cnt?<=?"00";
?????????AD7606_read?<=?'1';
?????????read_over?<=?'0';
??????ELSIF?(sys_clk'EVENT?AND?sys_clk?=?'1')?THEN
?????????CASE?current_state?IS
????????????WHEN?s_start?=>--開始狀態(tài)
???????????????AD7606_CS?<=?'1';
???????????????cvt_cnt?<=?"00";
???????????????AD7606_CVT_s?<=?'0';
???????????????AD7606_read?<=?'1';
???????????????read_over?<=?'0';
????????????WHEN?s_gen_cvt?=>--拉高CVT
???????????????IF?(cvt_cnt?<?"10")?THEN
??????????????????cvt_cnt?<=?cvt_cnt?+?"01";
???????????????ELSE
??????????????????AD7606_CVT_s?<=?'1';
??????????????????cvt_cnt?<=?"00";
???????????????END?IF;
????????????WHEN?s_rd_data?=>--cs使能信號(hào)
???????????????AD7606_CS?<=?'0';
????????????WHEN?s_sample_da?=>--讀數(shù)據(jù)
???????????????IF?(AD7606_read?=?'1')?THEN
??????????????????AD7606_read?<=?'0';--讀信號(hào)
???????????????ELSE
??????????????????AD7606_read?<=?'1';
???????????????END?IF;
???????????????IF?(channel_cnt?=?"111")?THEN--讀完
??????????????????read_over?<=?'1';
???????????????END?IF;
WHEN?OTHERS?=>NULL;
?????????END?CASE;
??????END?IF;
???END?PROCESS;
???
???--輸出AD采樣值
???PROCESS?(sys_clk,?reset)
???BEGIN
??????IF?(reset=?'0')?THEN
?????????channel_one?<=?"0000000000000000";
?????????channel_two?<=?"0000000000000000";
?????????channel_three?<=?"0000000000000000";
?????????channel_four?<=?"0000000000000000";
?????????channel_five?<=?"0000000000000000";
?????????channel_six?<=?"0000000000000000";
?????????channel_seven?<=?"0000000000000000";
?????????channel_eight?<=?"0000000000000000";
?channel_cnt?<=?"000";
??????ELSIF?(sys_clk'EVENT?AND?sys_clk?=?'1')?THEN
?????????IF(?current_state?=s_sample_da?)THEN
???????????????IF?(AD7606_read?=?'0')?THEN
??????????????????channel_cnt?<=?channel_cnt?+?"001";--計(jì)數(shù)
??????????????????CASE?channel_cnt?IS
?????????????????????WHEN?"000"?=>
????????????????????????channel_one?<=?AD7606_D;--通道1
?????????????????????WHEN?"001"?=>
????????????????????????channel_two?<=?AD7606_D;--通道2
?????????????????????WHEN?"010"?=>
????????????????????????channel_three?<=?AD7606_D;--通道3
?????????????????????WHEN?"011"?=>
????????????????????????channel_four?<=?AD7606_D;--通道4
?????????????????????WHEN?"100"?=>
????????????????????????channel_five?<=?AD7606_D;--通道5
?????????????????????WHEN?"101"?=>
????????????????????????channel_six?<=?AD7606_D;--通道6
?????????????????????WHEN?"110"?=>
????????????????????????channel_seven?<=?AD7606_D;--通道7
?????????????????????WHEN?"111"?=>
????????????????????????channel_eight?<=?AD7606_D;--通道8
??????????????????END?CASE;
???????????????END?IF;
?ELSE
channel_cnt?<=?"000";
END?IF;
??????END?IF;
???END?PROCESS;
???
--計(jì)數(shù)
???PROCESS?(sys_clk,?reset)
???BEGIN
??????IF?(reset=?'0')?THEN
?????????sample_cnt?<=?0;
??????ELSIF?(sys_clk'EVENT?AND?sys_clk?=?'1')?THEN
?????????IF?(sample_cnt?=?249)?THEN
????????????sample_cnt?<=?0;--計(jì)數(shù)到249
?????????ELSE
????????????sample_cnt?<=?sample_cnt?+?1;--計(jì)數(shù)
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--輸出
???AD7606_OS?<=?"000";--0
???AD7606_RST?<=?NOT?reset?;--取反???
???AD7606_CVT?<=?AD7606_CVT_s;
???AD7606_RD?<=?AD7606_read;
???sample_pulse?<=?'1'?when?(sample_cnt?=?249)?else?'0';--采樣
???
END?beh;

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=485